1. Field of the Invention
The invention relates to an integrated circuit for sampling a sequence of data packets at a data output, wherein each data packet appears in response to a request command. An important, but not exclusive, area of application is sampling the data read from memory cells in a memory.
2. Description of the Related Art
In order to transmit a binary data item which is queuing in a data source from the data source to a data output and to sample it there for the purpose of using it or forwarding it in clocked fashion, a request command is usually sent by a command issuer to a switching device, which is then closed and connects the data source to a data path routed to said data output. If a request command is used to request a packet comprising a plurality of parallel data bits, the switching device connects a corresponding number of parallel data paths to a data output which has an appropriate number of connections.
A “command path” routed from the command issuer to the switching device may contain line sections of greater or lesser length and discrete circuits, such as pulse shapers and demultiplexer stages for addressing the respective data source which is to be addressed. Equally, each data path may contain line sections and discrete circuits, such as amplifiers.
The chain of all the elements which are involved in the request for a respective data bit, that is to say the chain comprising the command path, the switching device and the data path, can be referred to as an “operating section” for the data request. As a result of the delays or transfer times on the elements in the command path and the data path and also the response time of the switching device, a certain time period elapses from the time at which the request command is sent up to the appearance of the requested data item at the data output, said time period subsequently being referred to as the “latency” of the operating section. It is necessary to wait for this latency before the requested data item can be sampled at the data output for further use. The sampling itself is usually done by triggering a sampling circuit arranged at the data output by means of a defined edge of a sampling pulse which is received via a control section with timing related to that of the request command.
Frequently, it is also desirable, prior to each sampling operation, to stipulate a time for making certain preparations which decide upon the further handling of the respective data item which is to be sampled. By way of example, this may be the conditioning of a demultiplexer which cyclically distributes successive data items from the data output over various routes. It may also be the conditioning of a parallel/series converter which routes individual bits of a packet comprising a plurality of parallel bits which appears at the data output onto the same bus in succession. An appropriate area of application is data sampling in a DDR-DRAM. In general, the signal stipulating the preparation time cannot become operative before the start of the relevant data item at the data output.
A method for taking account of the latency is to ensure a fixed waiting time between the time at which the request command is sent and the time of the sampling edge, e.g. using a timer or delay device which is operative in the control section and whose transfer time is set to a fixed value. However, the latency is not always constant, but rather can vary on the basis of production parameters, voltage and temperature, so that a fixed waiting time is not optimum.